1. Field of the Invention
The present invention generally relates to a memory circuit, and particularly relates to a nonvolatile memory circuit which is capable of retaining stored data in the absence of a power supply voltage.
2. Description of the Related Art
Nonvolatile semiconductor memory devices, which can retain stored data even when power is turned off, conventionally include flash EEPROM employing a floating gate structure, FeRAM employing a ferroelectric film, MRAMs employing a ferromagnetic film, etc. There is a new type of nonvolatile semiconductor memory device called PermSRAM. PermSRAM uses a pair of MIS (metal-insulating film-semiconductor) transistors as a nonvolatile memory cell (i.e., the basic unit of data storage). The MIS transistors used as a nonvolatile memory cell in PermSRAM have the same structure as ordinary MIS transistors used for conventional transistor functions (e.g., switching function), and do not require a special structure such as a floating gate or a special material such as a ferroelectric material or ferromagnetic material. The absence of such a special structure and special material offers an advantage in cost reduction. PermSRAM was initially disclosed in PCT/JP2003/016143, which was filed on Dec. 17, 2003, the entire contents of which are hereby incorporated by reference.
The MIS transistors used as a nonvolatile memory cell in PermSRAM are configured to experience an irreversible hot-carrier effect on purpose for storage of one-bit data. Here, the irreversible hot-carrier effect refers to the injection of electrons into the oxide film. A difference in the transistor characteristics caused by the hot-carrier effect represents one-bit data “0” or “1”. Such a difference may be detected as a difference in the ON current between the two transistors by using a sensing circuit such as a one-bit static memory circuit (latch) coupled to the MIS transistor pair.
Each memory cell unit of PermSRAM for storing on-bit data is comprised of a latch circuit and a nonvolatile memory cell. Data supplied from an external source to a PermSRAM are initially written to the latch circuits of the memory cell units corresponding to a selected row. After the writing of data to the latch circuits, a store operation is performed to transfer (copy) the data from the latch circuits to the respective nonvolatile memory cells. In each memory cell unit, the store operation causes a selected one of the two MIS transistors constituting the nonvolatile memory cell to experience a hot-carrier effect, and which one is selected depends on whether the data stored in the latch circuit is 0 or 1.
Such store operation may be performed on a row-by-row basis (i.e., word-line-specific basis), or may be performed with respect to all the memory cell units (i.e., with respect to the entirety of the PermSRAM). No mechanism has been provided in PermSRAM, however, to perform store operation on a column-by-column basis (i.e., bit-line-specific basis). In other words, no mask function that would allow some of the data bits stored in the latch circuits to be masked and not transferred to the nonvolatile memory cells has been available in PermSRAM.
There is thus a need for PermSRAM that is provided with a mask function.